Different techniques have been used to transfer data to and from memory (e.g., Synchronous Dynamic Random Access Memory (SDRAM)). One technique for transferring data to and from memory is Double Data Rate (DDR). DDR transfers data to and/from memory on leading and trailing edges of a clock signal or signals.
Differential clock signals are often used in DDR devices. The differential clock signals include a clock signal (e.g., CK and DQS) and its negative complement (e.g., CK# and DQS#). The differential clock signals generally have synchronized, opposite phases, so as one transitions from high-to-low, the other transitions from low-to-high, and they cross each other. To have adequate timing margin on writes to memory, the differential clock signals must meet a voltage input crossing (VIX) that is fairly tight. Ideally the transition crossing should occur within a certain VIX window usually centered about a reference point (VREF.) If the transition crossing does not occur within the VIX window, a timing penalty may occur and thus memory speed may be impaired.
Some type of voltage output crossing (VOX) control may be used to attempt to provide signals having transition crossings within the VIX window, but process, voltage, and/or temperature (PVT) driver timing variations may make it difficult to consistently maintain transition crossings within VIX limitation. For example, one method to maintain VOX control is to attempt to match all driver paths within the driver such that the clock to output (Tco) of a rising transition matches that of falling transition. This method fails because while it is possible to maintain the VOX at one PVT, the VOX may vary and not be within limits at other PVTs.
Modification of slew rate, through a process monitor, of the high-to-low and low-to-high transitions, has also been used to attempt to consistently maintain transition crossings within the VIX window. However, this method is often less than consistently accurate, for any number of reasons, including its potential for undesirably affecting signal integrity.